With the size reduction of electronic equipment, higher integration and further size reduction of a semiconductor device to be mounted therein have been required. Therefore, the system-in-package technology for densely packaging a plurality of semiconductor chips having integrated circuits formed therein and realizing a high-performance system in a short period of time has attracted attention and various packaging structures have been proposed.
For example, the development of a stacked package capable of achieving the size reduction by three-dimensionally stacking a plurality of semiconductor chips has been advanced. In the case of the stacked package, the stacked semiconductor chips are electrically connected by using a through electrode. The through electrode has a structure in which an electrode formed on a main surface (element forming surface, circuit forming surface) of a semiconductor substrate on which integrated circuits are formed and an electrode formed on a surface opposite to the main surface are connected via an electrode formed inside a through hole formed in the semiconductor substrate serving as a base material of the semiconductor chip.
Since a conventional semiconductor device has a structure in which several insulating layers and wiring layers are stacked on a main surface of a semiconductor substrate, exposure process is adopted only to a main surface side of the semiconductor substrate in the manufacturing process thereof. Therefore, even when the through electrode as described above is to be formed, the process from the main surface of the semiconductor substrate is performed.
For example, Japanese Patent Application Laid-Open Publication No. 2002-289623 (patent document 1) has disclosed a technique comprising the steps of: forming a hole and a trench surrounding the hole in a semiconductor substrate; forming a conductive material at least in the hole; forming an insulating material at least in the trench; and then removing a region on a rear surface side of the semiconductor substrate to expose the conductive material formed in the hole and the insulating material formed in the trench, thereby forming a conductive plug made of the conductive material formed in the hole and an insulating region made of the insulating material formed in the trench.
Also, Japanese Patent Application Laid-Open Publication No. 2007-53149 (patent document 2) has disclosed a technique comprising the steps of: forming a through hole whose opening has a cone shape from a rear surface of a semiconductor substrate; depositing an insulating film; removing a part of the insulating film to be a contact portion at the bottom of the through hole and forming a metal seed layer by sputtering; forming a metal layer by plating on a part of the metal seed layer including the through hole; and then processing the metal seed layer, thereby forming a pad and a wiring in the part including the through hole.